1. Technical Field
The present invention relates to a semiconductor device and a method of manufacturing the same, and in particular to a semiconductor device having silicide layers, and a method of manufacturing the same.
2. Related Art
There is known a conventional semiconductor device such as described in Japanese Laid-Open Patent Publication No. 2001-127270, describing formation of a semiconductor device of the embedded DRAM (dynamic random access memory), in which a silicide layer is formed over the entire surfaces of the DRAM section and the logic section, at a time in a single process step.
Nickel silicide has been becoming more popular as the silicide generally used for CMOS (complementary metal oxide semiconductor) device, rather than cobalt silicide and titanium silicide, as the elements are shrunk to a higher degree. This is because nickel silicide is superior to cobalt silicide, from the viewpoint of so-called thin wire effect, characterized by increase in sheet resistance under smaller gate length.
Adoption of nickel silicide is, however, more likely to cause junction leak as compared with cobalt silicide or the like. More specifically, nickel has the melting temperature lower than those of titanium and cobalt, and is therefore more reactive with the silicon composing the silicon substrate. Nickel atoms in the nickel silicide layer are more likely to diffuse across p-n junctions at the source/drain interfaces into the silicon substrate during annealing involved in the process of manufacturing. For this reason, adoption of nickel silicide with transistors provided in regions such as those in a DRAM section, under severe requirements in terms of suppression of junction leakage current, has been anticipated to cause current leakages possibly exceeding an allowable limit. It has therefore been difficult to adopt nickel silicide to the embedded DRAM device having transistors with a short gate length.
One known technique of improving this non-conformity is described in a pamphlet of International Patent WO 2003/96421. The literature describes a technique of forming a nickel silicide layer in transistors in the logic section, but providing no silicide layer to the transistors in the DRAM cell section. Providing no silicide layer to the transistors in the memory section, while providing silicide layer to the transistor in the peripheral circuit, is described also in Japanese Laid-Open Patent Publication No. 2005-191428.